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M41T82 M41T83
Serial I2C bus RTC with battery switchover
Features

Ultra-low battery supply current of 365 nA Factory calibrated accuracy 5 PPM guaranteed after 2 reflows (SOX18) - Much better accuracies achievable using built-in programmable analog and digital calibration circuits 2.0 V to 5.5 V clock operating voltage Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century Automatic switchover and reset output circuitry (fixed reference) - M41T83S VCC = 3.00 V to 5.50 V (2.85 V VRST 3.00 V) - M41T83R VCC = 2.70 V to 5.50 V (2.55 V VRST 2.70 V) - M41T83Z VCC = 2.38 V to 5.50 V (2.25 V VRST 2.38 V) Serial interface supports I C Bus (400 kHz protocol) Programmable alarm with interrupt function (valid even during battery back-up mode) Optional 2nd programmable alarm available Square wave output defaults to 32 KHz on power-up (M41T83 only) RESET (RST) output Watchdog timer Programmable 8-bit counter/timer 7 bytes of battery-backed user SRAM Battery low flag Power-down time stamp (HT bit) Low operating current of 80 A
2
QFN16, 4 mm x 4 mm (QA) (VFQFPN16)

18
1
SOX18 (MY, 18-pin, 300 mil SOIC with embedded crystal)
SO8 (M)

Oscillator stop detection Battery or Super-capTM back-up Operating temperature of -40C to 85C Package options include: - a 16-lead QFN (M41T83), - an 18-lead embedded crystal SOIC (M41T83), or - an 8-lead SOIC (M41T82) RoHS compliance: lead-free components are compliant with the RoHS directive

April 2008
Rev 7
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www.st.com 1
Contents
M41T82 M41T83
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 2.3 2.4 2.5
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Data retention and battery switchover (VSO = VRST) . . . . . . . . . . . . . . . . 20 Power-on reset (trec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 3.2 3.3 3.4 Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock/control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Real-time clock accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.1 3.4.2 Digital calibration (periodic counter correction) . . . . . . . . . . . . . . . . . . . 28 Analog calibration (programmable load capacitance) . . . . . . . . . . . . . . 30
3.5 3.6 3.7 3.8
Setting the alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Optional second programmable alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8-bit (countdown) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 Timer interrupt/timer pulse (TI/TP, M41T83 only) . . . . . . . . . . . . . . . . . 38 Timer flag (TF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Timer interrupt enable (TIE, M41T83 only) . . . . . . . . . . . . . . . . . . . . . . 39 Timer enable (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TD1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.9 3.10 3.11
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Square wave output (M41T83 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
M41T82 M41T83
Contents
3.12 3.13 3.14 3.15 3.16
Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Oscillator fail interrupt enable (M41T83 only) . . . . . . . . . . . . . . . . . . . . . . 42 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 OTP bit operation (M41T83 in SOX18 package only) . . . . . . . . . . . . . . . 43
4 5 6 7 8 9
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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List of tables
M41T82 M41T83
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 M41T82 clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Key to Table 2: M41T82 clock/control register map (32 bytes). . . . . . . . . . . . . . . . . . . . . . 24 M41T83 clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Key to Table 4: M41T83 clock/control register map (32 bytes). . . . . . . . . . . . . . . . . . . . . . 26 Digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Analog calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Timer control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Interrupt operation (bit TI/TP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Timer source clock frequency selection (244.1 s to 4.25 hrs). . . . . . . . . . . . . . . . . . . . . . 39 Timer countdown value register bits (addr 11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Initial power-on default values (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Initial power-up default values (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 QFN16 - 16-lead, quad, flat package, no lead, 4 x 4 mm mech. data . . . . . . . . . . . . . . . . 51 SOX18 - 18-lead plastic small outline, 300 mils, embedded crystal, package mech. . . . . 53 SO8 - 8-lead plastic small outline (150 mils body width), package mech. data . . . . . . . . . 54 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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M41T82 M41T83
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. M41T82 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 M41T83 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SO8 (M) connections (M41T82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 QFN16 (QA) connections (M41T83) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SOX18 (MY) connections (M41T83). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 M41T82 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 M41T82 hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 M41T83 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 M41T83 hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Internal load capacitance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Clock accuracy vs. on-chip load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Clock divider chain and calibration circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Back-up mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Measurement AC I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ICC2 vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Bus timing requirement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 QFN16 - 16-lead, quad, flat package, no lead, 4 x 4 mm body size outline . . . . . . . . . . . 51 QFN16 - 16-lead, quad, flat package, no lead, 4 x 4 mm, recommended footprint . . . . . . 52 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SOX18 - 18-lead plastic small outline, 300 mils, embedded crystal, outline . . . . . . . . . . . 53 SO8 - 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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Description
M41T82 M41T83
1
Description
The M41T8x are low power serial I2C real-time clocks with a built-in 32.768 kHz oscillator (external crystal-controlled for the QFN16 and SO8 packages, embedded crystal for the SOX18 package). Eight bytes of the Register Map (see Table 2 on page 23) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 17 bytes of the Register Map provide status/control of the two Alarms, Watchdog, 8-bit Counter, and Square Wave functions. An additional seven bytes are made available as user SRAM. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T8x has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the clock operations can be supplied by a small lithium button battery when a power failure occurs. Functions available to the user include a non-volatile, time-of-day clock/calendar, two Alarm interrupts, Watchdog Timer, programmable 8-bit Counter, and Square Wave outputs. The eight clock address locations contain the century, year, month, date, day, hour, minute, second, and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. The M41T83 is supplied in either a QFN16 (QA) or an SOX18 (MY), 300mil SOIC which includes an embedded 32 KHz crystal. The SOX18 package requires only a user-supplied battery to provide non-volatile operation. The M41T82 is available only in an SO8 package.
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M41T82 M41T83 Figure 1. M41T82 logic diagram
VBAT VCC
Description
XI XO FT/RST SDA SCL (1)
VSS
AI11196
1. Open drain
Figure 2.
M41T83 logic diagram
VBAT VCC
XI(1) XO(1) SDA SCL
SQW(2) IRQ1/OUT/FT(3) RST(3) IRQ2(3)
VSS
AI11195
1. For QFN16 package only. 2. Defaults to 32 KHz on power-up. 3. Open drain
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Description Table 1. Signal names
Description 32KHz oscillator input 32KHz oscillator output
M41T82 M41T83
Symbol XI(1) XO(1) IRQ1/OUT/FT SQW(2) RST FT/RST IRQ2
(3)
Interrupt 1/output driver/frequency test output (open drain) 32KHz programmable square wave output Power-on reset output (open drain) Frequency test output/power-on reset (open drain - M41T82 only) Interrupt for alarm 2 (open drain) Serial data address input/output Serial clock input Battery supply voltage (tie VBAT to VSS if no battery is connected.) Do not use Supply voltage Ground
SDA SCL VBAT DU(4) VCC VSS
1. For SO8 and QFN16 packages only. 2. Defaults to 32 KHz on power-up. 3. For SOX18 and QFN16 packages only. 4. DU pin must be tied to VCC.
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M41T82 M41T83 Figure 3. SO8 (M) connections (M41T82)
XI XO VBAT VSS 1 2 3 4 8 7 6 5 VCC FT/RST(1) SCL SDA
AI11199
Description
M41T82
1. Open drain output
Figure 4.
QFN16 (QA) connections (M41T83)
XO VCC NC XI
16 RST (1) 1 2
15
14
13 12 11 IRQ2 (1) (1)
NC NC SQW (2)
IRQ1/FT/OUT SCL SDA
M41T83 3 4 5
VBAT
10 9 6
VSS
7
NC
8
NC
AI11197
1. Open drain output 2. Defaults to 32 Hz on power-up.
Figure 5.
SOX18 (MY) connections (M41T83)
NC NF(1) NF(1) NC (2) RST DU(3) SQW(4) VBAT VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 NC (1) NF NF(1) VCC IRQ2(2) NC (2) IRQ1/FT/OUT SCL SDA
AI11198
M41T83
1. NF pins must be tied to VSS. Pins 2 and 3, and 16 and 17 are internally shorted together. 2. Open drain output 3. Do not use (must be tied to VCC) 4. Defaults to 32 KHz on power-up.
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Description Figure 6. M41T82 block diagram
REAL TIME CLOCK CALENDAR OSCILLATOR FAIL CIRCUIT ALARM1 ALARM2 WATCHDOG 2 IC INTERFACE FT
M41T82 M41T83
XI CRYSTAL 32KHz OSCILLATOR XO
SDA
SCL WRITE PROTECT VCC < VRST
FREQUENCY TEST OUTPUT DRIVER 8-BIT COUNTER USER SRAM (7 Bytes)
INTERNAL POWER VCC
VBAT COMPARE trec TIMER
VRST/VSO(1)
(2) RST
AI11812
1. VRST = VSO = 2.93 V (S), 2.63 V (R), and 2.32 V (Z). 2. Open drain output
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M41T82 M41T83 Figure 7.
VCC
Description M41T82 hardware hookup
M41T82 VCC XI XO VBAT VSS SCL SDA (1) FT/RST VCC
MCU
Reset Input
Serial Clock Line Serial Data Line
AI11813
1. Open drain output
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Description Figure 8. M41T83 block diagram
REAL TIME CLOCK CALENDAR OSCILLATOR FAIL CIRCUIT ALARM1 ALARM2 WATCHDOG 2 IC INTERFACE FT OUT TIE SQWE OFIE A1IE A2IE
M41T82 M41T83
XI CRYSTAL 32KHz OSCILLATOR XO
IRQ2
(1) (1)
SDA
IRQ1/FT/OUT
SCL WRITE PROTECT VCC < VRST
FREQUENCY TEST OUTPUT DRIVER 8-BIT COUNTER SQUARE WAVE 8 BITS OF OTP USER SRAM (7 Bytes)
SQW
INTERNAL POWER VCC
VBAT COMPARE trec TIMER
VRST/VSO(2)
RST(1)
AI11800
1. Open drain output 2. VRST = VSO = 2.93 V (S), 2.63 V (R), and 2.32 V (Z).
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M41T82 M41T83 Figure 9. M41T83 hardware hookup
Description
VCC
M41T83 VCC IRQ1/FT/OUT (1) RST (1) XO IRQ2 XI VBAT VSS (1) VCC INT
MCU
Reset Input Port Serial Clock Line Serial Data Line 32KHz CLKIN
AI11801
SCL SDA SQW
1. Open drain output
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Operation
M41T82 M41T83
2
Operation
The M41T8x clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 32 bytes contained in the device can then be accessed sequentially in the following order:

1st byte: tenths/hundredths of a second register 2nd byte: seconds register 3rd byte: minutes register 4th byte: century/hours register 5th byte: day register 6th byte: date register 7th byte: month register 8th byte: year register 9th byte: digital calibration register 10th byte: watchdog register 11th - 15th bytes: alarm 1 registers 16th byte: flags register 17th byte: timer value register 18th byte: timer control register 19th byte: analog calibration register 20th byte: square wave register 21st - 25th bytes: alarm 2 registers 26th - 32nd bytes: user RAM
The M41T8x clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VRST, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out-of-tolerance system. The power input will also be switched from the VCC pin to the battery when VCC falls below the battery back-up switchover voltage (VSO = VRST). At this time the clock registers will be maintained by the attached battery supply. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC.
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M41T82 M41T83
Operation
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:

Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is High. Changes in the data line, while the clock line is High, will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain High.
2.1.2
Start data transfer
A change in the state of the data line, from high to Low, while the clock is High, defines the START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves."
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Operation
M41T82 M41T83
2.1.5
Acknowledge
Each byte of eight bits is followed by one Acknowledge bit. This Acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition. Figure 10. Serial bus data transfer sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
Figure 11. Acknowledgement sequence
CLOCK PULSE FOR ACKNOWLEDGEMENT 1 2 8 9
START SCL FROM MASTER
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
16/58
M41T82 M41T83
Operation
2.2
Read mode
In this mode the master reads the M41T8x slave after setting the slave address (see Figure 13 on page 18). Following the WRITE Mode control bit (R/W = 0) and the Acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ Mode control bit (R/W = 1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge clock. The M41T8x slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to "An+2." This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume due to a Stop Condition or when the pointer increments to any non-clock address (08h-1Fh).
Note:
This is true both in READ Mode and WRITE Mode. An alternate READ Mode may also be implemented whereby the master reads the M41T8x slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 14 on page 18). Figure 12. Slave address location
R/W
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
17/58
Operation Figure 13. Read mode sequence
START START R/W
M41T82 M41T83
BUS ACTIVITY: MASTER
SDA LINE
S
WORD ADDRESS (An)
ACK
S
R/W
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS
STOP
DATA n+X
P
AI00899
Figure 14. Alternative read mode sequence
START STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
AI00895
BUS ACTIVITY: MASTER SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
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R/W
NO ACK
ACK
M41T82 M41T83
Operation
2.3
Write mode
In this mode the master transmitter transmits to the M41T8x slave receiver. Bus protocol is shown in Figure 15. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address "An" will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T8x slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see Figure 12 on page 17 and again after it has received the word address and each data byte.
Figure 15. Write mode sequence
START STOP
BUS ACTIVITY: MASTER
R/W
SDA LINE
S
WORD ADDRESS (An)
ACK ACK
DATA n
DATA n+1
DATA n+X
P
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00591
ACK
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Operation
M41T82 M41T83
2.4
Data retention and battery switchover (VSO = VRST)
Once VCC falls below the switchover voltage (VSO = VRST), the device automatically switches over to the battery and powers down into an ultra low current mode of operation to preserve battery life. If VBAT is less than, or greater than VRST, the device power is switched from VCC to VBAT when VCC drops below VRST (see Figure 25 on page 48). At this time the clock registers and user RAM will be maintained by the attached battery supply. When it is powered back up, the device switches back from battery to VCC at VSO + hysteresis. When VCC rises above VRST, it will recognize the inputs. For more information on battery storage life refer to Application Note AN1012.
2.5
Power-on reset (trec)
The M41T8x continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST output pulls low (open drain) and remains low after power-up for trec (210 ms typical) after VCC rises above VRST (max).
Note:
The trec period does not affect the RTC operation. Write protect only occurs when VCC is below VRST. When VCC rises above VRST, the RTC will be selectable immediately. Only the RST output is affected by the trec period. The RST pin is an open drain output and an appropriate pull-up resistor to VCC should be chosen to control the rise time.
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M41T82 M41T83
Clock operation
3
Clock operation
The M41T8x is driven by a quartz-controlled oscillator with a nominal frequency of 32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The 8-byte clock register (see Table 2 on page 23 and Table 4 on page 25) is used to both set the clock and to read the date and time from the clock, in binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a '0' the oscillator restarts within one second (typical).
Note:
Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST bit to '0.' This provides an additional "kick-start" to the oscillator circuit. Bits D6 and D7 of clock register 03h (century/ hours register) contain the CENTURY bit 0 (CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The ninth clock register is the digital calibration register, while the analog calibration register is found at address 12h (these are both described in the clock calibration section). For the M41T83, bit D7 of register 09h (Watchdog register) contains the Oscillator Fail Interrupt Enable bit (OFIE). When the user sets this bit to '1,' any condition which sets the Oscillator Fail bit (OF) (see Section 3.13: Oscillator fail detection on page 42) will also generate an interrupt output.
Note:
A WRITE to ANY location within the first eight bytes of the clock register (00h-07h), including the ST bit and CB0-CB1 bits will result in an update of the system clock and a reset of the divider chain. This could result in an inadvertent change of the current time. These non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. The eight clock registers may be read one byte at a time, or in a sequential block. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.
3.1
Power-down time-stamp
When a power failure occurs, the Halt Update bit (HT) will automatically be set to a "1". This will prevent the clock from updating the clock registers, and will allow the user to read the exact time of the power-down event. Resetting the HT bit to a "0" will allow the clock to update the clock with the current time. For more information, see Application note AN1572.
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Clock operation
M41T82 M41T83
3.2
Clock/control register map
The M41T8x offers 32 internal registers which contain clock, calibration (digital and analog), Alarm 1 and 2, Watchdog, Flags, Timer, and Square Wave (M41T83 only). The clock registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM TIMEKEEPER(R) cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address (00h to 07h). The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer increments to a non-clock address. Clock and alarm registers store data in BCD format. Calibration, Timer, Watchdog, and Square Wave bits are written in a binary format.
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M41T82 M41T83 Table 2.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h-1Fh TE ACS 0 0 RPT24 RPT23 RPT22 RPT21 0 AC6 0 0 RPT25 0 0 AC5 0 0 0 0 0 RPT14 RPT13 RPT12 RPT11 WDF ST 0 CB1 0 0 0 CB0 0 0 0 0 10 years FT BMB4 0 RPT15 HT DCS BMB3 ABE DC4 BMB2 Al1 10M DC3 BMB1 0 10 date 10M D6 D5 D4 D3 D2 D1 D0 0.1 seconds 10 seconds 10 minutes 10 hours 0 0 0.01 seconds seconds minutes Hours (24 hour format) Day of week Date: day of month Month Year DC2 BMB0 DC1 RB1 DC0 RB0
Clock operation
M41T82 clock/control register map (32 bytes)(1)
Function/range BCD format seconds seconds minutes Century/hours Day Date Month Year Digital calibration Watchdog Al1 month Al1 date Al1 hour Al1 min Al1 sec 0 Flags Timer value 0 AC2 0 TD1 AC1 AL2E TD0 AC0 0 Timer control Analog calibration SQW SRAM/Al2 month SRAM/Al2 date SRAM/Al2 hour SRAM/Al2 min SRAM/Al2 sec SRAM 01-12 01-31 00-23 00-59 00-59 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 0-3/00-23 01-7 01-31 01-12 00-99
Alarm1 month Alarm1 date Alarm1 hour Alarm1 minutes Alarm1 seconds TF OF 0
AI1 10 date AI1 10 hour
Alarm1 10 minutes Alarm1 10 seconds AF1 AF2
(2)
BL
Timer countdown value 0 AC4 0 Al2 10M 0 AC3 0
Alarm2 month Alarm2 month Alarm2 date Alarm2 minutes Alarm2 seconds
AI2 10 date AI2 10 hour
Alarm2 10 minutes Alarm2 10 seconds User SRAM (7 bytes)
1. See Table 3: Key to Table 2: M41T82 clock/control register map (32 bytes) 2. AF2 will always read `0', if the AL2E bit is set to `0'.
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Clock operation Table 3.
M41T82 M41T83 Key to Table 2: M41T82 clock/control register map (32 bytes)
Code Explanation Must be set to zero Alarm in battery back-up enable bit Analog calibration bits Analog calibration sign bit Alarm flag bits Alarm 2 enable bit Battery low bit Watchdog multiplier bits Century bits Digital calibration bits Digital calibration Sign bit Frequency test bit Halt update bit Oscillator fail bit Watchdog resolution bits Alarm 1 repeat mode bits Alarm 2 repeat mode bits Stop bit Timer frequency bits Timer enable bit Timer flag Watchdog flag
0 ABE AC0-AC6 ACS AF1, AF2 AL2E BL BMB0-BMB4 CB0, CB1 DC0-DC4 DCS FT HT OF RB0-RB2 RPT11-RPT15 RPT21-RPT25 ST TD0, TD1 TE TF WDF
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M41T82 M41T83 Table 4.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h1Fh TE ACS RS3 A2IE RPT24 RPT23 RPT22 RPT21 TI/TP AC6 RS2 0 RPT25 0 TIE AC5 RS1 0 OUT OFIE A1IE RPT14 RPT13 RPT12 RPT11 WDF ST 0 CB1 0 0 0 CB0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0
Clock operation
M41T83 clock/control register map (32 bytes)(1)
Function/range BCD format seconds seconds Minutes Century/hours Day Date Month Year DC1 RB1 DC0 RB0 Digital calibration Watchdog Al1 month Al1 date Al1 hour Al1 min Al1 sec 0 Flags Timer value 0 AC2 0 TD1 AC1 AL2E TD0 AC0 OTP Timer control Analog calibration SQW SRAM/Al2 month SRAM/Al2 date SRAM/Al2 hour SRAM/Al2 min SRAM/Al2 sec SRAM 01-12 01-31 00-23 00-59 00-59 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 0-3/00-23 01-7 01-31 01-12 00-99
0.1 seconds 10 seconds 10 minutes 10 hours 0 10 date 10M 0 0
0.01 seconds seconds Minutes Hours (24 hour format) Day of week Date: day of month Month Year DC4 BMB2 Al1 10M DC3 BMB1 DC2 BMB0
10 years FT BMB4 SQWE RPT15 HT DCS BMB3 ABE
Alarm 1month Alarm1 date Alarm1 hour Alarm1 minutes Alarm1 seconds TF OF 0
AI1 10 date AI1 10 hour
Alarm1 10 minutes Alarm1 10 seconds AF1 AF2(2) BL
Timer countdown value 0 AC4 RS0 Al2 10M 0 AC3 0
Alarm2 month Alarm2 date Alarm2 hour Alarm2 minutes Alarm2 seconds
AI2 10 date AI2 10 hour
Alarm2 10 minutes Alarm2 10 seconds User SRAM (7 bytes)
1. See Table 5: Key to Table 4: M41T83 clock/control register map (32 bytes). 2. AF2 will always read `0', if the AL2E bit is set to `0'.
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Clock operation Table 5.
M41T82 M41T83 Key to Table 4: M41T83 clock/control register map (32 bytes)
Code Explanation Must be set to zero Alarm in battery back-up enable bit Alarm interrupt enable bits Analog calibration bits Analog calibration sign bit Alarm flag Alarm 2 enable bit Battery low bit Watchdog multiplier bits Century bits Digital calibration bits Digital calibration Sign bit Frequency test bit Halt update bit Oscillator fail bit Output level Oscillator fail interrupt enable OTP control bit Watchdog resolution bits Alarm 1 repeat mode bits Alarm 2 repeat mode bits SQW frequency Square wave enable SRAM/alarm 2 bit Stop bit Timer frequency bits Timer enable bit Timer flag Timer interrupt or pulse Timer interrupt enable Watchdog flag
0 ABE A1IE, A2IE AC0-AC6 ACS AF1, AF2 AL2E BL BMB0-BMB4 CB0, CB1 DC0-DC4 DCS FT HT OF OUT OFIE OTP RB0-RB2 RPT11-RPT15 RPT21-RPT25 RS0-RS3 SQWE SRAM/ALM2 ST TD0, TD1 TE TF TI/TP TIE WDF
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M41T82 M41T83
Clock operation
3.3
Real-time clock accuracy
The M41T8x is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The accuracy of the real-time clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Temperature also affects the crystal frequency, causing additional error (see Figure 17 on page 31). The M41T8x provides the option of clock correction through either manufacturing calibration or in-application calibration. The total possible compensation is typically -93 ppm to +156 ppm. The two compensation circuits that are available are: 1. An Analog Calibration register (12h) can be used to adjust internal (on-chip) load capacitors for oscillator capacitance trimming. The individual load capacitors CXI and CXO (see Figure 16), are selectable from a range of -18 pF to +9.75 pF in steps of 0.25 pF. This translates to a calculated compensation of approximately 30 ppm (see Section 3.4.2: Analog calibration (programmable load capacitance) on page 30). A Digital Calibration register (08h) can also be used to adjust the clock counter by adding or subtracting a pulse at the 512 Hz divider stage. This approach provides periodic compensation of approximately -63 ppm to +126 ppm (see Section 3.4.1: Digital calibration (periodic counter correction) on page 28).
2.
Figure 16. Internal load capacitance adjustment
XI CXI Crystal Oscillator XO CXO
AI11804
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Clock operation
M41T82 M41T83
3.4
Clock calibration
The M41T8x oscillator is designed for use with a 12.5 pF crystal load capacitance. When the calibration circuit is properly employed, accuracy improves to better than 1 ppm at 25C. The M41T8x design provides the following two methods for clock error correction.
3.4.1
Digital calibration (periodic counter correction)
This method employs the use of periodic counter correction by adjusting the ratio of the 100 Hz divider stage to the 512 Hz divider stage. Under normal operation, the 100 Hz divider stage outputs precisely 100 pulses for every 512 pulses of the 512 Hz input stage to provide the input frequency to the Fraction of Seconds Clock register. By adjusting the number of 512 Hz input pulses used to generate 100 output pulses, the clock can be sped up or slowed down, as shown in Figure 19 on page 34. When a non-zero value is loaded into the five Calibration bits (DC4 - DC0) found in the Digital Calibration Register (08h) and the sign bit is `1', (indicating positive calibration), the 100Hz stage outputs 100 pulses for every 511 input pulses instead of the normal 512. Since the 100 pulses are now being output in a shorter window, this has the effect of speeding up the clock by 1/512 seconds for each second the circuit is active. Similarly, when the sign bit is `0', indicating negative calibration, the block outputs 100 pulses for every 513 input pulses. Since the 100 pulses are then being output in a longer window, this has the effect of slowing down the clock by 1/512 seconds for each second the circuit is active. The amount of calibration is controlled by using the value in the calibration register (N) to generate the adjustment in one second increments. This is done for the first N seconds once every eight minutes for positive calibration, and for N seconds once every sixteen minutes for negative calibration (see Table 6 on page 29). For example, if the Calibration register is set to '100010,' then the adjustment will occur for two seconds in every minute. Similarly, if the calibration register is set to '000011,' then the adjustment will occur for 3 seconds in every alternating minute. The Digital Calibration bits (DC4 - DC0) occupy the five lower order bits in the Digital Calibration Register (08h). These bits can be set to represent any value between 0 and 31 in binary form. The sixth bit (DCS) is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within an 8-minute (positive) or 16-minute (negative) cycle. Therefore, each calibration step has an effect on clock accuracy of +4.068 or -2.034 ppm. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month, which corresponds to a total range of +5.5 or -2.75 minutes per month.
Note:
1
The modified pulses are not observable on the Frequency Test (FT) output, nor will the effect of the calibration be measurable real-time, due to the periodic nature of the error compensation. Positive digital calibration is performed on an eight minute cycle, therefore the value in the calibration register should not be modified more frequently than once every eight minutes for positive values of calibration. Negative digital calibration is performed on a sixteen minute cycle, therefore negative values in the calibration register should not be modified more frequently than once every sixteen minutes.
2
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M41T82 M41T83 Table 6. Digital calibration values
Clock operation
Calibration value (binary) DC4 - DC0 0 (00000) 1 (00001) 2 (00010) 3 (00011) 4 (00100) 5 (00101) 6 (00110) 7 (00111) 8 (01000) 9 (01001) 10 (01010) 11 (01011) 12 (01100) 13 (01101) 14 (01110) 15 (01111) 16 (10000) 17 (10001) 18 (10010) 19 (10011) 20 (10100) 21 (10101) 22 (10110) 23 (10111) 24 (11000) 25 (11001) 26 (11010) 27 (11011) 28 (11100) 29 (11101) 30 (11110) 31 (11111)
Calibration value rounded to the nearest ppm Negative calibration (DCS = 0) Positive calibration (DCS = 1) 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -31 -33 -35 -37 -39 -41 -43 -45 -47 -49 -51 -53 -55 -57 -59 -61 -63 0 4 8 12 16 20 24 28 33 37 41 45 49 53 57 61 65 69 73 77 81 85 90 94 98 102 106 110 114 118 122 126
N
N/491520 (per minute)
N/245760 (per minute)
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Clock operation
M41T82 M41T83
3.4.2
Analog calibration (programmable load capacitance)
A second method of calibration employs the use of programmable internal load capacitors to adjust (or trim) the oscillator frequency. By design, the oscillator is intended to be 0 ppm crystal accuracy at room temperature (25C, see Figure 17 on page 31). For a 12.5 pF crystal, the default loading on each side of the crystal will be 25 pF. For incrementing or decrementing the calibration value, capacitance will be added or removed in increments of 0.25 pF to each side of the crystal. Internally, CLOAD of the oscillator is changed via two digitally controlled capacitors, CXI and CXO, connected from the XI and XO pins to ground (see Figure 16 on page 27). The effective on-chip series load capacitance, CLOAD, ranges from 3.5 pF to 17.4 pF, with a nominal value of 12.5 pF (AC0-AC6 = `0'). The effective series load capacitance (CLOAD) is the combination of CXI and CXO: C LOAD = 1 ( 1 C XI + 1 C XO ) Seven analog calibration bits, AC0 to AC6, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the RTC. Each bit has a different weight for capacitance adjustment. An Analog Calibration Sign (ACS) bit determines if capacitance is added (ACS bit = `0', negative calibration) or removed (ACS bit = `1', positive calibration). The majority of the calibration adjustment is positive (i.e. to increase the oscillator frequency by removing capacitance) due to the typical characteristic of quartz crystals to slow down due to changes in temperature, but negative calibration is also available. Since the Analog Calibration Register adjustment is essentially "pulling" the frequency of the oscillator, the resulting frequency changes will not be linear with incremental capacitance changes. The equations which govern this mechanism indicate that smaller capacitor values of Analog Calibration adjustment will provide larger increments. Thus, the larger values of Analog Calibration adjustment will produce smaller incremental frequency changes. These values typically vary from 6-10 ppm/bit at the low end to <1 ppm/bit at the highest capacitance settings. The range provided by the Analog Calibration Register adjustment with a typical surface mount crystal is approximately 30 ppm around the AC6-AC0 = 0 default setting because of this property (see Table 7 on page 31).
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M41T82 M41T83 Figure 17. Crystal accuracy across temperature
Clock operation
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = K x (T - T )2 O F
2 2 K = -0.036 ppm/C 0.006 ppm/C
TO = 25C 5C
Temperature C
AI07888
Table 7.
Analog calibration values
Analog calibration value D7 D6 D5 D4 D3 D2 D1 D0 CXI, CXO CLOAD(1)
Addr
ACS () 0pF 3pF 5pF 12h -7pF 9.75pF(2)) -18pF(3) 1 0 1 x 0 0
AC6 (16pF) 0 0 0 0 0 1
AC5 (8pF) 0 0 0 0 1 0
AC4 (4pF) 0 0 1 1 0 0
AC3 (2pF) 0 1 0 1 0 1
AC2 (1pF) 0 1 1 1 1 0
AC1
AC0
(0.5pF) (0.25pF) 0 0 0 0 1 0 0 0 0 0 1 0 25pF 28pF 30pF 18pF 34.75pF 7pF
1/2(CXI, CXO) 12.5pF 14pF 15pF 9pF 17.4pF 3.5pF
1. CLOAD = 1/(1/CXI + 1/CXO) 2. Maximum negative calibration value 3. Maximum positive calibration value
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Clock operation
M41T82 M41T83
The on-chip capacitance can be calculated as follows: 1 C LOAD = -- [ ( AC6 - AC0 value, decimal) x 0.25pF ] + 25pF 2 For example:

CLOAD (12h = x0000000) = 12.5 pF, CLOAD (12h =11001000) = 3.5 pF, and CLOAD (12h = 00100111) = 17.4 pF.
The oscillator sees a minimum of 3.5 pF with no programmable load capacitance selected. Note: These are typical values, and the total load capacitance seen by the crystal will include approximately 1-2 pF of package and board capacitance in addition to the Analog Calibration register value. Any invalid value of Analog Calibration will result in the default capacitance of 25 pF. The combination of analog and digital trimming can give up to -93 to +156 ppm of the total adjustment. Figure 18 on page 33 represents a typical curve of clock ppm adjustment versus the Analog Calibration value. This curve may vary with different crystals, so it is good practice to evaluate the crystal to be used with an M41T8x device before establishing the adjustment values for the application in question.
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M41T82 M41T83 Figure 18. Clock accuracy vs. on-chip load capacitance
Clock operation
100.0
XI XO Crystal Oscillator
80.0
PPM ADJUSTMENT
60.0 40.0
CXI
CXO
CLOAD =
20.0
FASTER DECREASING LOAD CAP.
CXI * CXO CXI + CXO
On-Chip
INCREASING LOAD CAP.
0.0
SLOWER
-20.0 OFFSET TO CXI, C XO (pF) NET EQUIV. LOAD CAP., C LOAD , (pF) Analog Calibration Value, AC, register 0x12 -18.0 -15.0 3.5 5.0 -10.0 7.5 0xA8 -5.0 10 0x94 0.0 12.5 0x00 5.0 15 0x14 9.75 17.4 0x27
0xC8 0xBC
ai13906
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Clock operation
M41T82 M41T83
Two methods are available for ascertaining how much calibration a given M41T8x may require:
The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses either or both of the Calibration bytes. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ1/FT/OUT pin. The IRQ1/FT/ OUT pin will toggle at 512Hz when FT and OUT bits = '1' (M41T83 only) and ST = '0.' Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring either a -10 (xx001010) to be loaded into the Digital Calibration byte, or +6 pF (00011000) into the Analog Calibration byte for correction.
Note:
Setting or changing the Digital Calibration byte does not affect the Frequency Test, Square Wave, or Watchdog Timer frequency, but changing the Analog Calibration byte DOES affect all functions derived from the low current oscillator (see Figure 19). Figure 19. Clock divider chain and calibration circuits
512Hz Output Frequency Test /2 CXI 32KHz Low Current Oscillator /8 CXO Digital Calibration Circuitry (divide by 511/512/513) 1Hz Signal Analog Calibration Circuitry Clock Registers /2 /2 /2 /2 Remainder of Divider Circuit Square Wave Watchdog Timer 8-bit Timer
AI11806c
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M41T82 M41T83 Figure 20. Crystal isolation example
Crystal Local Grounding Plane (Layer 2)
Clock operation
XI XO
VSS
AI11814
1. Substrate pad should be tied to VSS.
3.5
Setting the alarm clock registers
Address locations 0Ah-0Eh (Alarm 1) and 14h-18h (Alarm 2) contain the alarm settings. Either alarm can be configured independently to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. Bits RPT15-RPT11 and RPT25-RPT21 put the alarms in the repeat mode of operation. Table 8 on page 37 shows the possible bit configurations. Codes not listed in the table default to the once-per-second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT15-RPT11 and/or RPT25-RPT21, AF1 (Alarm 1 Flag) or AF2 (Alarm 2 Flag) is set. If A1IE (Alarm 1 Interrupt Enable), or A2IE (Alarm 2 Interrupt Enable) are also set, the alarm condition activates either the IRQ1/FT/OUT, or IRQ2 output pins. To disable either of the alarms, write a '0' to the Alarm Date Registers and to the RPTx5-RPTx1 bits.
Note:
If the address pointer is allowed to increment to the Flag Register address, or the last address written is "Alarm Seconds," the address pointer will increment to the Flag address, and an alarm condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a different address. The IRQ output is cleared by a READ to the Flags Register (0Fh) as shown in Figure 21. A subsequent READ of the Flags Register is necessary to see that the value of the Alarm Flag has been reset to '0'.
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Clock operation
M41T82 M41T83
3.6
Optional second programmable alarm
When the Alarm 2 Enable (AL2E) bit (D1 of address 13h) is set to a logic `1', registers 14h through 18h provide control for a second programmable alarm which operates in the same manner as the alarm function described above. The A2IE (Alarm 2 Interrupt Enable) bit allows the second alarm to trigger a separate interrupt output (IRQ2). The AL2E bit defaults on initial power-up to a logic `0' (Alarm 2 disabled). In this mode, the five address bytes (14h-18h) function as additional user SRAM, for a total of 12 bytes of user SRAM. The IRQ1/FT/OUT pin can also be activated in the battery back-up mode (see Figure 22 on page 36). Figure 21. Alarm interrupt reset waveform
0Eh 0Fh 00h
ALARM FLAG BITS (AFx)
IRQ1/FT/OUT or IRQ2
HIGH-Z
AI08898
Figure 22. Back-up mode alarm waveform
VCC VPFD VSO trec AF Bit in Flags Register IRQ1/FT/OUT or IRQ2 HIGH-Z
AI09164c
1. ABE and A1IE bits = 1.
36/58
M41T82 M41T83 Table 8.
RPT5 1 1 1 1 1 0
Clock operation Alarm repeat modes
RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm setting Once per second Once per minute Once per hour Once per day Once per month Once per year
3.7
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog Register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3*1, or 3 seconds). If the processor does not reset the timer within the specified period, the M41T8x sets the WDF (Watchdog Flag) and generates a watchdog interrupt. The watchdog timer can be reset by having the microprocessor perform a WRITE of the Watchdog Register. The time-out period then starts over. Should the watchdog timer time-out, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ1/FT/OUT pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the Flags Register will reset the Watchdog Flag (bit D7; Register 0Fh). The watchdog function is automatically disabled upon power-up and the Watchdog Register is cleared. If the watchdog function is set, the frequency test function is activated, and the SQWE bit is '0,' the watchdog function prevails and the frequency test function is denied.
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Clock operation
M41T82 M41T83
3.8
8-bit (countdown) timer
The Timer Value Register is an 8-bit binary countdown timer. It is enabled and disabled via the Timer Control Register (11h) TE bit. Other timer properties such as the source clock, or interrupt generation are also selected in the Timer Control Register (see Table 9). For accurate read back of the countdown value, the I2C-bus clock (SCL) must be operating at a frequency of at least twice the selected timer clock. The Timer Control register selects one of four source clock frequencies for the timer (4096, 64, 1, or 1/60 Hz), and enables/disables the timer. The timer counts down from a softwareloaded 8-bit binary value. At the end of every countdown, the timer sets the Timer Flag (TF) bit. The TF bit can only be cleared by software. When asserted, the timer flag (TF) can also be used to generate an interrupt (IRQ1/FT/OUT) on the M41T83. The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of TF. The Timer Interrupt/Timer Pulse (TI/TP) bit is used to control this mode selection. When reading the timer, the current countdown value is returned. Table 9.
Addr 0Fh 10h 11h TE TI/TP TIE
Timer control register map(1)
D7 WDF D6 AF1 D5 AF2 D4 BL D3 TF D2 OF D1 0 D0 0 Function Flags Timer value 0 TD1 TD0 Timer control
Timer countdown value 0 0
1. Bit positions labeled with `0' should always be written with logic '0.'
3.8.1
Timer interrupt/timer pulse (TI/TP, M41T83 only)
TI/TP = 0 IRQ1/FT/OUT is active when TF is logic '1' (subject to the status of the Timer Interrupt Enable bit (TIE).
TI/TP = 1 IRQ1/FT/OUT pulses are active when TF is logic '1' according to Table 10 (subject to the status of the TIE bit).
Note:
If an Alarm condition, Watchdog time-out, Oscillator Failure, or OUT = 0 causes IRQ1/FT/OUT to be asserted low, then IRQ1/FT/OUT will remain asserted even if TI/TP is set to '1'. When in pulse mode (TI/TP = 1), clearing the TF bit will not stop the pulses on IRQ1/FT/OUT. The output pulses will only stop if TE, TIE, or TI/TP are reset to '0'.
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M41T82 M41T83 Table 10. Interrupt operation (bit TI/TP = 1)
IRQ(1) periods Source clock (Hz) 4096 64 1 1/60 n(2) = 1 1/8192 1/128 1/64 1/64
Clock operation
n>1 1/4096 1/64 1/64 1/64
1. TF and IRQ1/FT/OUT become active simultaneously. 2. n = loaded countdown timer value. The timer is stopped when n = 0.
3.8.2
Timer flag (TF)
At the end of a timer countdown, TF is set to logic '1.' If both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading the flag bits. The timer will auto-reload and continue to count down regardless of the state of TF bit (or TI/TP bit). The TF bit is cleared by reading the Flags Register.
3.8.3
Timer interrupt enable (TIE, M41T83 only)
In Level mode (TI/TP = 0), when TF is asserted, the interrupt is asserted (if TIE = 1). To clear the interrupt, the TF bit or the TIE bit must be reset.
3.8.4
Timer enable (TE)

TE = 0 When the Timer Register (10h) is set to `0', the timer is disabled. TE = 1 The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the counter will begin from the same value as when it was disabled.
3.8.5
TD1/0
These are the timer source clock frequency selection bits (see Table 11). These bits determine the source clock for the countdown timer (see Table 12). When not in use, the TD1 and TD0 bits should be set to `11' (1/60 Hz) for power saving. Table 11. Timer source clock frequency selection (244.1 s to 4.25 hrs)
TD1 0 0 1 1 TD0 0 1 0 1 Timer source clock frequency (Hz) 4096 (244.1 s) 64 (15.6 ms) 1 (1 s) 1/60 (60 s)
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Clock operation Table 12.
Bit 7-0
M41T82 M41T83 Timer countdown value register bits (addr 11h)(1)
Symbol Countdown period = n / source clock frequency. Description This register holds the loaded countdown value `n'.
1. Writing to the timer register will not reset the TF bit or clear the interrupt.
3.9
Square wave output (M41T83 only)
The M41T83 offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 13. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the Square Wave Enable bit (SQWE) located in Register 0Ah.
Note:
If the SQWE bit is set to '1' and VCC falls below the switchover (VSO) voltage, the square wave output will be disabled. Table 13. Square wave output frequency
Square wave bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Square wave Frequency None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units - kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
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M41T82 M41T83
Clock operation
3.10
Battery low warning
The M41T8x automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The Battery Low (BL) bit, bit D4 of Flags Register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity. Clock data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. The M41T8x only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
3.11
Century bits
These two bits will increment in a binary fashion at the turn of the century, and handle all leap years correctly. See Table 14 for additional explanation. Table 14. Century bits examples
CB1 0 1 0 1 Leap Year? Yes No No No Example(1) 2000 2100 2200 2300
CB0 0 0 1 1
1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not).
3.12
Output driver pin
When the OFIE bit, A1IE bit, and Watchdog Register are not set to generate an interrupt, the IRQ1/FT/OUT pin becomes an output driver that reflects the contents of D7 of register 08h. In other words, when D7 (OUT bit) is a '0,' then the IRQ1/FT/OUT pin will be driven low.
Note:
The IRQ1/FT/OUT pin is an open drain which requires an external pull-up resistor.
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Clock operation
M41T82 M41T83
3.13
Oscillator fail detection
If the Oscillator Fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time. This bit can be used to judge the validity of the clock and date data. This bit will be set to '1' any time the oscillator stops. In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the oscillator. The following conditions can cause the OF bit to be set:
The first time power is applied (defaults to a '1' on power-up).
Note:
If the OF bit cannot be written to '1' 4 seconds after the initial power-up, the STOP bit (ST) should be written to a '1,' then immediately reset to '0.'

The voltage present on VCC or battery is insufficient to support oscillation. The ST bit is set to '1.' External interference of the crystal
For the M41T83, if the Oscillator Fail Interrupt Enable bit (OFIE) is set to a '1,' the IRQ1/FT/OUT pin will also be activated. The IRQ1/FT/OUT output is cleared by resetting the OFIE or OF bit to '0' (NOT by reading the Flag Register). The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have run for at least 4 seconds before attempting to reset the OF bit to '0.' If the trigger event occurs during a power down condition, this bit will be set correctly.
3.14
Oscillator fail interrupt enable (M41T83 only)
If the Oscillator Fail Interrupt Enable bit (OFIE) is set to a '1,' the IRQ1/FT/OUT pin will also be activated. The IRQ1/FT/OUT output is cleared by resetting the OFIE or OF bit to '0' (not by reading the Flags Register).
3.15
Initial power-on defaults
Upon initial application of power to the device, the register bits will initially power-on in the state indicated in Table 15 and Table 16.
Table 15.
Initial power-on default values (part 1)
ST CB1 CB0 OUT FT DCS Digital Analog OFIE Watchdog A1IE SQWE ABE (2) (3) (2) (2) ACS calib. calib. 0 UC 0 UC 0 UC 0 UC 0 0 0 UC 1 UC 0 UC
Condition(1) Initial Power-up Subsequent Power-up(4) (5)
0 UC
0 UC
0 UC
1 UC
0 0
1. All other control bits power-up in an undetermined state. 2. M41T83 only. 3. BMB0-BMB4, RB0, RB1. 4. With battery back-up. 5. UC = unchanged.
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M41T82 M41T83 Table 16. Initial power-up default values (part 2)
RPT11-15 HT OF TE TI/TP TIE
(2) (2)
Clock operation
Condition(1) Initial Power-up Subsequent Power-up(3) (4)
TD1 TD0 RS0 RS1-3
OTP A2IE
(2) (2)
RPT2125 0 UC
AL2E
0 UC
1 1
1 UC
0 0
0 UC
0 UC
1 UC
1 UC
1 UC
0 UC
0 UC
0 UC
0 UC
1. All other control bits power-up in an undetermined state. 2. M41T83 only. 3. With battery back-up. 4. UC = unchanged.
3.16
OTP bit operation (M41T83 in SOX18 package only)
When the OTP (One Time Programmable) bit is set to a '1,' the value in the internal OTP registers will be transferred to the analog calibration register (12h) and are "Read only." The OTP value is programmed by the manufacturer, and will contain the calibration value necessary to achieve 5 ppm at room temperature after two SMT reflows. This clock accuracy can then be guaranteed to drift no more than 3 ppm the first year, and 1 ppm for each following year due to crystal aging. If the OTP bit is set to '0,' the analog calibration register will become a WRITE/READ register and function like standard SRAM memory cells, allowing the user to implement any desired value of analog calibration. When the user sets the OTP bit, they need to wait for approximately 8 ms before the analog registers transfer the value from the OTP to the analog registers due to the OTP Read operation.
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Maximum ratings
M41T82 M41T83
4
Maximum ratings
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 17.
Sym TSTG VCC TSLD(2)
Absolute maximum ratings
Parameter Storage temperature (VCC off, Oscillator off) Supply voltage QFN16 260 Lead solder temperature for 10 seconds SO8 SOX18 245 -0.2 to Vcc+0.3 20 1 C V mA W C Value(1) -55 to 125 -0.3 to 7.0 Unit C V
VIO IO PD
Input or output voltages Output current Power dissipation
1. Data based on characterization results, not tested in production. 2. Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
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M41T82 M41T83
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 18. Operating and AC measurement conditions(1)
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages
1. Output Hi-Z is defined as the point where data is no longer driven.
M41T8x 2.38 V to 5.5 V -40 to 85C 50 pF 5 ns 0.2 VCC to 0.8 VCC 0.3 VCC to 0.7 VCC
Figure 23. Measurement AC I/O waveform
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 19.
Symbol CIN COUT(3) tLP
Capacitance
Parameter(1,2) Input capacitance Output capacitance Low-pass filter input time constant (SDA and SCL) Min Max 7 10 50 Unit pF pF ns
1. Effective capacitance measured with power supply at 3.6V; sampled only, not 100% tested. 2. At 25C, f = 1 MHz. 3. Outputs deselected.
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DC and AC parameters Table 20.
Sym
M41T82 M41T83
DC characteristics
Parameter Test condition(1) -40 to 85C -40 to 85C -40 to 85C 0V VIN VCC 0V VOUT VCC 5.5 V 125 55 45 8 6.5 -0.3 0.7VCC RST, FT/RST VCC/VBAT = 3.0 V, IOL = 1.0 mA VCC = 3.0 V, IOL = 1.0 mA VCC = 3.0 V, IOL = 3.0 mA 2.4 5.5 2.5 2.0 25C; VCC = 0 V; OSC On; VBAT = 3 V; 32 KHz Off 365 5.5 5.5 450 0.3VCC VCC+0.3 0.4 0.4 0.4 10 SCL = 400kHz (No load) Min 3.00 2.70 2.38 Typ Max 5.50 5.50 5.50 1 1 150 Unit V V V A A A A A A A V V V V V V V V V nA
Operating voltage (S) VCC Operating voltage (R) Operating voltage (Z) ILI ILO Input leakage current Output leakage current
ICC1
Supply current
3.0 V 2.5 (Z only)
ICC2
SCL = 0Hz; All inputs VCC - 0.2 V or Supply current (standby) VSS + 0.2 V (SQWE bit = 0) Input low voltage Input high voltage
5.5 V 3.0 V
VIL VIH
VOL
Output low voltage
SQW, IRQ1/FT/OUT SCL, SDA
VOH
Output high voltage Pull-up supply voltage (open drain)
VCC = 3.0 V, IOH = -1.0 mA (push-pull) IRQ1/FT/OUT
VBAT VCAP IBAT
Battery back-up supply voltage(2) Capacitor back-up supply voltage Battery supply current
1. Valid for ambient operating temperature: TA = -40 to 85C; VCC = 2.38 V to 5.5 V (except where noted). 2. For non-rechargeable Lithium battery.
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M41T82 M41T83 Figure 24. ICC2 vs. temperature
DC and AC parameters
10.000
9.000
8.000
7.000
Icc2 (A)
6.000
(3.0V) (5.0V)
5.000
4.000
3.000
2.000 -40
-20
0
20 Temperature (C)
40
60
80
ai 13909
Table 21.
Symbol fO RS CL
Crystal electrical characteristics
Parameter(1)(2) Resonant frequency Series resistance Load capacitance 12.5 Min Typ 32.768 65(3) Max Units kHz k pF
1. Externally supplied if using the QFN16 or SO8 package. STMicroelectronics recommends the Citizen CFS145 (1.5x5mm) and the KDS DT-38 (3 x 8 mm) for thru-hole, or the KDS DMX-26S (3.2x8mm) or Micro Crystal MS3V-T1R (1.5x5mm) for surface-mount, tuning fork-type quartz crystals. For contact information, see Section 8: References on page 56. 2. Load capacitors are integrated within the M41T8x. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 3. Guaranteed by design.
Table 22.
Symbol VSTA tSTA CXI, CXO(1)
Oscillator characteristics
Parameter(1)(2) Oscillator start voltage Oscillator start time Capacitor input, capacitor output IC-to-IC frequency variation
(2)(3)
Conditions 4s VCC = VSO
Min 2.0
Typ
Max
Units V
1 25 -10 +10
s pF ppm
1. With default analog calibration value ( = 0). 2. Reference value. 3. TA = 25C, VCC = 5.0 V.
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DC and AC parameters Figure 25. Power down/up mode AC waveforms
VCC VSO tPD SDA SCL DON'T CARE
M41T82 M41T83
trec
AI00596
Table 23.
Sym
Power down/up trip points DC characteristics
Parameter(1) (2) (1,2) S Min 2.85 2.55 2.25 Typ 2.93 2.63 2.32 VRST 25 140 2.5 280 Max 3.0 2.7 2.38 Unit V V V V mV ms s
VRST
Reset threshold voltage
R Z
Battery back-up switchover VSO Hysteresis Reset Pulse width (VCC rising) trec VCC to Reset Delay, VCC = (VRST + 100 mV), falling to (VRST - 100 mV; for VCC slew rate of 10 mV/s
1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = -40 to 85C; VCC = 2.38 to 5.5 V (except where noted).
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M41T82 M41T83 Figure 26. Bus timing requirement sequence
DC and AC parameters
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:ST tF tHD:STA
AI00589
Table 24.
Sym fSCL tLOW tHIGH tR tF tHD:STA tSU:STA
AC characteristics
Parameter(1) SCL clock frequency Clock low period Clock high period SDA and SCL rise time SDA and SCL fall time START condition hold time (after this period the first clock pulse is generated) START condition setup time (only relevant for a repeated start condition) 600 600 100 0 600 1.3 Min 0 1.3 600 300 300 Typ Max 400 Units Hz s ns ns ns ns ns ns s ns s
tSU:DAT(2) Data setup time tHD:DAT tSU:STO tBUF Data hold time STOP condition setup time Time the bus must be free before a new transmission can start
1. Valid for ambient operating temperature: TA = -40 to 85C; VCC = 2.38 to 5.5 V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
49/58
Package mechanical information
M41T82 M41T83
6
Package mechanical information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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M41T82 M41T83
Package mechanical information
Figure 27. QFN16 - 16-lead, quad, flat package, no lead, 4 x 4 mm body size outline
D
E
A3
A1
A
ddd C
b L
e
1 2
E2
3
D2
QFN16-A
1. Drawing is not to scale.
Table 25.
Sym
QFN16 - 16-lead, quad, flat package, no lead, 4 x 4 mm mech. data
mm Typ Min 0.80 0.00 - 0.25 3.90 2.50 3.90 2.50 - 0.30 0.08 Max 1.00 0.05 - 0.35 4.10 2.80 4.10 2.80 - 0.50 - Typ 0.035 0.001 0.008 0.012 0.157 - 0.157 - 0.026 0.016 - inches Min 0.031 0.000 - 0.010 0.154 0.098 0.154 0.098 - 0.012 0.003 Max 0.039 0.002 - 0.014 0.161 0.110 0.161 0.110 - 0.020 -
A A1 A3 b D D2 E E2 e L ddd
0.90 0.02 0.20 0.30 4.00 - 4.00 - 0.65 0.40 -
51/58
Package mechanical information
M41T82 M41T83
Figure 28. QFN16 - 16-lead, quad, flat package, no lead, 4 x 4 mm, recommended footprint
2.70 0.70 0.20
4.50
2.70
0.35 0.325 0.65
AI11815
1. Dimensions are shown in millimeters (mm).
Figure 29. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data
6.0 0.2
3.2 VSOJ2 0
1.5
SMT CRYSTAL
7.0 0.3
15 XI 16 XO 14 13
1
3.9
2 3 4
ST QFN16
3.9
AI11816
1. Dimensions shown are in millimeters (mm).
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M41T82 M41T83
Package mechanical information
Figure 30. SOX18 - 18-lead plastic small outline, 300 mils, embedded crystal, outline
D
9 1
h x 45
C E H
10
18
A2 B SO-J e A1
A ddd A1 L
1. Drawing is not to scale.
Table 26.
SOX18 - 18-lead plastic small outline, 300 mils, embedded crystal, package mech.
millimeters inches Max 2.69 0.31 2.39 0.51 0.31 11.66 7.67 10.52 - 0.81 Typ 0.101 0.009 0.092 0.018 0.010 0.457 0.300 0.407 0.050 0.026 Min 0.096 0.006 0.090 0.016 0.008 0.455 0.298 0.400 - 0.020 Max 0.106 0.012 0.094 0.020 0.012 0.459 0.302 0.414 - 0.032
Symbol Typ A A1 A2 B c D E E1 e L 2.57 0.23 2.34 0.46 0.25 11.61 7.62 10.34 1.27 0.66 Min 2.44 0.15 2.29 0.41 0.20 11.56 7.57 10.16 - 0.51
53/58
Package mechanical information Figure 31. SO8 - 8-lead plastic small package outline
M41T82 M41T83
h x 45 h x 45 A2
A2
A
B
A
b e
ccc
e D ddd
c
C
D
0.25 mm GAUGE PLANE k
8
8
E1
1
1
EE
H
A1
L L1
A1
L
SO-A
SO-A
1. Drawing is not to scale.
Table 27.
SO8 - 8-lead plastic small outline (150 mils body width), package mech. data
mm inches Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 0.25 0 0.40 1.04 5.00 6.20 4.00 0.50 8 0.127 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 0.010 0 0.016 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 0.020 8 0.050 Typ Min Max 0.069 0.010
Symb Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
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M41T82 M41T83
Part numbering
7
Part numbering
Table 28.
Example:
Ordering information
M41T 83 S QA 6 E
Device family M41T
Device type 82 (SO8 package only) 83
Operating voltage S = VCC = 3.00 to 5.5 V R = VCC = 2.70 to 5.5 V Z = VCC = 2.38 to 5.5 V
Package QA = QFN16 (4 mm x 4 mm) M(1) = SO8 MY(2)= SOX18
Temperature range 6 = -40C to 85C
Shipping method E = ECOPACK(R) package, tubes F = ECOPACK(R) package, tape & reel
1. M41T82 only. 2. The SOX18 package includes an embedded 32,768 Hz crystal.
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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References
M41T82 M41T83
8
References
Below is a listing of the crystal component suppliers mentioned in this document.

KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp. Citizen can be contacted at csd@citizen-america.com or http://www.citizencrystal.com. Micro Crystal can be contacted at sales@microcrystal.ch or http://www.microcrystal.com.
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Revision history
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Table 29.
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Revision history
Document revision history
Revision 1 First edition Updated package mechanical data in Figure 31: SO8 - 8-lead plastic small package outline and Table 27: SO8 - 8-lead plastic small outline (150 mils body width), package mech. data; small text changes for entire document, amended footnotes in Table 1, Table 14 and Figure 5. Document status upgraded to full datasheet; added footnote to diagram in Features; amended footnotes in Figure 2 and updated footnotes in Table 28; updated `typical data' for ICC1 and ICC2 in Table 20; Updated package mechanical data for the QFN16 and SOX18 in Section 6; changed kHz to KHz through document; made small text changes throughout document. Updated cover page (features and amended footnote concerning availability), Figure 18: Clock accuracy vs. on-chip load capacitance, and ordering information (Table 28). Updated title of product (added I2C bus) on cover page; updated Section 3.16, Section 3.4.1, Table 17, 20, 28, Figure 29; added Figure 24; added Micro Crystal information (Table 21). Updated Features on cover page; minor formatting changes; modified footnote 1 in Table 21; added Section 8: References. Updated cover page. Changes
27-Jul-2006
17-Oct-2006
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19-Dec-2006
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08-Mar-2007
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08-May-2007
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12-Nov-2007 17-Apr-2008
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